NXP Semiconductors
PCA9531
8-bit I 2 C-bus LED dimmer
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9531, which will be stored in the Control register.
0
0
0
AI
0
B2
B1
B0
Auto-Increment flag
register address
002aac506
Reset state: 00h
Fig 6.
Control register
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment ?ag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rollover to ‘000’ after the last register
is accessed.
When Auto-Increment ?ag is set (AI = 1) and a read sequence is initiated, the sequence
must start by reading a register different from the Input register (B2 B1 B0 ≠ 0 0 0).
Only the 3 least signi?cant bits are affected by the AI ?ag. Unused bits must be
programmed with zeroes.
6.2.1 Control register de?nition
Table 3.
Register summary
B2
0
0
0
0
1
1
1
B1
0
0
1
1
0
0
1
B0
0
1
0
1
0
1
0
Symbol
INPUT
PSC0
PWM0
PSC1
PWM1
LS0
LS1
Access
read only
read/write
read/write
read/write
read/write
read/write
read/write
Description
input register
frequency prescaler 0
PWM register 0
frequency prescaler 1
PWM register 1
LED0 to LED3 selector
LED4 to LED7 selector
6.3 Register descriptions
6.3.1 INPUT - Input register
The INPUT register re?ects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Table 4.
INPUT - Input register description
Bit
Symbol
Default
7
LED7
X
6
LED6
X
5
LED5
X
4
LED4
X
3
LED3
X
2
LED2
X
1
LED1
X
0
LED0
X
Remark: The default value ‘X’ is determined by the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to V DD .
PCA9531_6
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 19 February 2009
6 of 27
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